RIS CUTTING EDGE FOURM
Advanced Cryptographic Hardware Acceleration
先进密码硬件加速
Advanced Cryptographic Hardware Acceleration
- RISTA CUTTING EDGE FORUM Season 5 Session 3
- Time：8pm-9pm, May 7th, 2026.
- Speaker guest：Prof.Yingxue Gao
- Chair guest：Prof.Teng Wang
With the rapid advancement of quantum computing technology, traditional cryptographic algorithms face the risk of being quickly compromised. Post-quantum cryptography, which can effectively resist quantum computing attacks, has become a research hotspot in the field of cryptography. Post-quantum cryptographic algorithms encompass various types based on different security problems, each involving multiple kinds of operators. In response to key challenges such as high computational complexity in the hardware deployment of post-quantum cryptography, this report first systematically introduces the hardware architecture implementation methods for core operators of post-quantum cryptography. Second, it elaborates on circuit-level design techniques for post-quantum cryptography. Finally, it provides an in-depth discussion on overall hardware architecture implementation schemes for post-quantum cryptography. Through the above content, this report aims to offer systematic reference and technical support for the design of hardware accelerators for post-quantum cryptography.
Gao Yingxue received her Ph.D. from the University of Science and Technology of China. She is currently an Associate Professor at the School of Integrated Circuit Science and Technology, Nanjing University of Posts and Telecommunications. Her research interests include intelligent processor chip architecture design, hardware acceleration for post-quantum cryptography, and fault-tolerant hardware architecture design. She has published papers in prestigious international journals and conferences such as TCAD, TC, DAC, DATE, and FPL. To date, she has authored or co-authored a total of 11 papers, including 8 as the first author, among which 5 are CCF-A papers and 2 are CCF-B papers. She is a recipient of the CAS President's Award and was selected for the Outstanding Doctoral Dissertation Award by the CCF Technical Committee on Integrated Circuit Design. She currently serves as an Executive Member of the CCF Technical Committee on Fault-Tolerant Computing, a TPC Member of the DAC Conference, and a TPC Member of the 2026 CCF Chip Conference. She has also been invited to serve as a reviewer for international journals including TVLSI, TCBB, TCASI, FITEE, and OJCAS.
Related
